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Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
DESCRIPTION
The AM6012 12-bit multiplying Digital-to-Analog converter provides high-speed and 0.025% differential nonlinearity over its full commercial temperature range. The D/A converter uses a 3-bit segment generator for the MSBs in conjunction with a 9-bit R-2R diffused resistor ladder to provide 12-bit resolution without costly trimming processes. This technique guarantees a very uniform step size (up to LSB from the ideal), monotonicity to 12 bits and integral nonlinearity to 0.05% at its differential current outputs. The dual complementary outputs of the AM6012 increase its versatility, and effectively double the peak-to-peak output swing. Digital inputs, in addition, can be configured to accept all popular logic families. While the device requires a reference input of 1mA for a 4mA full-scale current, operation is nearly independent of power supply voltage shifts. The power supply rejection ratio is 0.001% FS/% V. The devices will work from +5, -12V to 18V rails, with as low as 230mW power consumption typical.
PIN CONFIGURATION
D1 and F Packages
D1 D2 D3 D4 D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 20 V+ 19 I O 18 I O 17 V- 16 COMP 15 V REF(-) 14 VREF(+) 13 GND/V LC 12 D LSB
12
D10 10
11 D 11
TOP VIEW
NOTE: 1. Available in large SO (SOL) package only.
APPLICATIONS FEATURES
* 12-bit resolution * Accurate to within 0.05% * Monotonic over temperature * Fast settling time, 250ns typical * Trimless design for low cost * Differential current outputs * High-speed multiplying capability * Full-scale current, 4mA (with 1mA reference) * High output compliance voltage, -5 to +10V * Low power consumption, 230mW
ORDERING INFORMATION
DESCRIPTION 20-Pin Ceramic Dual In-Line Package (CERDIP) 20-Pin Plastic Small Outline Large (SOL) Package
* CRT displays, computer graphics * Robotics and machine tools * Automatic test equipment * Programmable power supplies * CAD/CAM systems * Data acquisition and control systems * Analog-to-digital converter systems
TEMPERATURE RANGE 0 to +70C 0 to +70C
ORDER CODE AM6012F AM6012D
DWG # 0584B 0172D
August 31, 1994
776
853-0904 13721
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
BLOCK DIAGRAM
V(+) 20 GND/MSB VLC B1 13 1 B2 2 B3 3 B4 4 B5 5 B6 6 B7 7 b8 8 B9 9 B10 10 B11 11 LSB B12 12
DECODER BIAS NETWORK REFERENCE AMPLIFIER CURRENT SWITCHES
LOGIC SWITCHES 18 19
IO IO
VREF (+)
14
VREF (-)
15 9-SEGMENT GENERATOR
ISEG
9-BIT R-2R D/A CONVERTER
16 COMP
17 V(-)
ABSOLUTE MAXIMUM RATINGS
SYMBOL TA TSTG TSOLD VS Operating temperature AM6012F Storage temperature range Lead soldering temperature 10sec max Power supply voltage Logic inputs Voltage across current outputs VREF VREF IREF PD Reference inputs V14, V15 Reference input differential voltage (V14 to V15) Reference input current (I14) Maximum power dissipation, TA=25C, (still-air)1 F package D package NOTES: 1. Derate above 25C, at the following rate: F package at 12.5mW/C D package at 11.1mW/C 1560 1390 mW mW 0 to +70 -65 to +150 300 18 -5V to +18 -8V to +12 V- to V+ 18 1.25 V mA C C C V V V PARAMETER RATING UNIT
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Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
DC ELECTRICAL CHARACTERISTICS
V+=+15V, V-=-15V, IREF=1.0mA, 0C TA 70C SYMBOL PARAMETER Resolution Monotonicity DNL NL IFS TCIFS Differential nonlinearity Nonlinearity Full-scale current Full-scale tempco DNL Specification guaranteed over compliance range ROUT>10M typ. IFS-IFS Deviation from ideal step size 12 Deviation from ideal straight line VREF=10.000V R14-R15=10.000k TA=25C 3.935 3.999 10 0.001 VOC IFSS IZS VIL VIH Output voltage compliance Symmetry Zero-scale current Logic input levels Logic input current Logic input swing Reference current range Reference bias current Reference input slew rate Power supply sensitivity Power supply range R14(eq)=800 CC=0pF V+=+13.5V to +16.5V, V-=-15V V-=-13.5V to -16.5V, V+=+15V VOUT=0V V+=+5V, V-=-15V Power supply current V+=+15V, V-=-15V Power dissipation V+=+5V, V-=-15V V+=+15V, V-=-15V 4.5 -18 5.7 -13.7 5.7 -13.7 234 291 Logic "0" Logic "1" IIN VIS IREF I15 dl/dt PSSIFS+ PSSIFSV+ VI+ II+ IPD VIN=-5 to +18V V-=-15V -5 0.2 0 4.0 1.0 -0.5 8.0 0.0005 0.00025 0.001 0.001 18 -10.8 8.5 -18.0 8.5 -18.0 312 397 mW mA V 2.0 40 +18 1.1 -2.0 A V mA A mA/s %FS/% -5 0.4 .05 4.063 40 0.004 +10 2.0 0.10 0.8 TEST CONDITIONS LIMITS Min 12 12 0.025 Typ Max UNIT Bits Bits %FS Bits %FS mA ppm/C %FS/C V A A V
AC ELECTRICAL CHARACTERISTICS
V+=+15V, V-=-15V, IREF=1.0mA, 0C TA 70C SYMBOL tS tPLH tPHL COUT PARAMETER Settling time Propagation delay--all bits Output capacitance TEST CONDITIONS To 1/2LSB, all bits ON or OFF, TA=25C 50% to 50% LIMITS Min Typ 250 25 20 Max 500 50 UNIT ns ns pF
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778
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
CIRCUIT DESCRIPTION
The AM6012 is a 12-bit DAC which uses diffused resistors and requires no trimming to guarantee monotonicity over the temperature range. A segmented DAC design guarantees a more uniform step size over the temperature range than is normally available with trimmed 12-bit converters. The converter features differential high compliance current outputs, wide supply range, and a multiplying reference input. In many converter applications, uniform step size is more important than conformance to an ideal straight line. Many 12-bit converters are used for high resolution rather than high linearity, since few transducers are more linear than 0.1%. All classic binarily weighted converters require 1/2LSB (0.012%) linearity in order to guarantee monotonicity, which requires very tight resistor matching and tracking. The AM6012 uses conventional bipolar processing to achieve high differential linearity and monotonicity without requiring correspondingly high linearity, or conformance to an ideal straight line. One design approach which provides monotonicity without requiring high linearity is the MOS switch-resistor string. This circuit is actually a full complement to a current-switched R-2R DAC since it is slower, has a voltage output, and, if implemented at the 12-bit level, would use 4096 low tolerance resistors rather than a minimum number of high tolerance resistors as in the R-2R network. Its lack of speed and density for 12 bits are its drawbacks. With the segmented DAC approach, the 4096 required output levels are composed of 8 groups of 512 steps each. Each step group is generated by a 9-bit DAC, and each of the segment slopes is determined by one of 8 equal current sources. The resistors which determine monotonicity are in the 9-bit DAC. The major carry of the 9-bit DAC is repeated in each of the 8 segments, and requires eight times lower initial resistor accuracy and tracking to maintain a given differential nonlinearity over temperature. The operation of the segmented DAC may be visualized by assuming an input code of all zeroes. The first segment current IO is divided into 512 levels by the 9-bit multiplying DAC and fed to the output, IOUT. As the input code increases, a new segment current is selected for each 512 counts. The previous segment is fed to output IOUT where the new step group is added to it, thus ensuring monotonicity independent of segment resistor values. All higher order segments feed IOUT. With the segmented DAC approach, the precision of the 8 main resistors determines linearity only. The influence of each of these resistors on linearity is four times lower than that of the MSB resistor in an R-2R DAC. Hence, assuming the same resistor tolerances for both, the linearity of the segmented approach would actually be higher than that of an R-2R design. The step generator or 9-bit DAC is composed of a master and a slave ladder. The slave ladder generates the four least significant bits from the remainder of the master ladder by active current
splitting utilizing scaled emitters. This saves ladder resistors and greatly reduces the range of emitter scaling required in the 9-bit DAC. All current switches in the step generator are high-speed fully-differential switches which are capable of switching low currents at high speed. This allows the use of a binary scaled network all the way to the least significant bit which saves power and simplifies the circuitry. Diffused resistors have advantages over thin film resistors beyond simple economy and bipolar process compatibility. The resistors are fabricated in single crystal rather than amorphous material which gives them better long term stability and tracking and much higher moisture resistance. They are diffused at 1000C and so are resistant to changes in value due to thermal and chemical causes. Also, no burn-in is required for stability. The contact resistance between aluminum and silicon is more predictable than between aluminum and an amorphous thin film, and no sandwich metals are required to enhance or protect the contact or limit alloying. The initial match between two diffused resistors is similar to that of thin film since both are defined by photomasks and chemical etching. Since the resistors are not trimmed or altered after fabrication, their tracking and long-term characteristics are not degraded.
DIFFERENTIAL VS INTEGRAL NONLINEARITY
Integral nonlinearity, for the purposes of the discussion, refers to the "straightness" of the line drawn through the individual response points of a data converter. Differential nonlinearity, on the other hand, refers to the deviation of the spacing of the adjacent points from a 1 LSB ideal spacing. Both may be expressed as either a percentage of full-scale output or as fractional LSBs or both. The graphs in Figure 1 define the manner in which these parameters are specified. The left graph shows a portion of the transfer curve of a DAC with 1/2LSB INL and the (implied) DNL spec of 1 LSB. Below this is a graphic representation of the way this would appear on a CRT screen where the AM6012 is used as a display driver. On the right is a portion of the transfer curve of a DAC specified for 1/2LSB INL with LSB DNL specified and the graphic display below it. One of the characteristics of an R-2R DAC in standard form is that any transition which causes a zero LSB change (i.e., the same output for two different codes) will exhibit the same output each time that transition occurs. The same holds true for transitions causing a 2 LSB change. These two problem transitions are allowable for the standard definition of monotonicity and also allow the device to be specified very tightly for INL. The major problem arising from this error type is in A/D converter implementations. Inputs producing the same output are now represented by ambiguous output codes for an identical input. Also, two LSB gaps can cause large errors at those input levels (assuming 1/2LSB quantizing levels). It can be seen from the two figures that the DNL-specified D/A converter will yield much finer grained data than the INL-specified part, thus improving the ability of the A/D to resolve changes in the analog input.
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779
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
DIFFERENTIAL LINEARITY COMPARISON
+1/2LSB LIMIT IDEAL OUTPUTS ACUTAL OUTPUTS ANALOG OUT 2LSB CHANGE ON X011-X100 TRANSITION SEGMENT OF 12-BIT DAC TRANSFER CURVE FOR: INL = 1/2LSB DNL = 1LSB NO CHANGE ON XX01-XX10 TRANSITION -1/2LSB LIMIT 0000 0010 0100 0110 1000 1010 1100 1110 0001 0011 0101 0111 1001 1011 1101 1111 DIGITAL INPUT SEGMENT CHANGE IDEAL OUTPUTS ACUTAL OUTPUTS SEGMENT CHANGE +2LSB LIMIT -2 LSB LIMIT
ANALOG OUT
SEGMENT OF 12-BIT DAC TRANSFER CURVE FOR: INL = 2LSB DNL = 2LSB 0010 0010 0100 0110 1000 1010 1100 1110 0001 0011 0101 0111 1001 1011 1101 1111 DIGITAL INPUT
1/2LSB INL, 1LSB DNL
2LSB INL, 1LSB DNL
Figure 1. Differential Linearity Comparison
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided where IO+IO=IFR. Current appears at the "true" output when a "1" is applied to each logic input. As the binary count increases, the sink current at Pin 18 increases proportionally, in the fashion of a "positive logic" D/A converter. When a "0" is applied to any input bit, that current is turned off at Pin 18 and turned on at Pin 19. A decreasing logic count increases IO as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required, it must still be connected to ground or to a point capable of sourcing IFR; do not leave an unused output pin open. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance is 25V above Vand is independent of the positive supply. Negative compliance is +10V above V-. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers.
compliance, reference amplifier negative common-mode range, negative logic input range, and negative logic threshold range; consult the various figures for guidance. For example, operation at -9V with IREF=1mA is not recommended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible, however at least 8V total must be applied to insure turn-on of the internal bias network. Symmetrical supplies are not required, as the AM6012 is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required; however, an artificial ground may be used to insure logic swings, etc., remain between acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the AM6012 are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is tight, typically 10ppm/C, with zero-scale output current and drift essentially negligible compared to 1/2LSB. The temperature coefficient of the reference resistor R14 should match and track that of the output resistor for minimum overall full-scale drift.
POWER SUPPLIES
The AM6012 operates over a wide range of power supply voltages from a total supply of 20V to 36V. When operating with V- supplies of -10V or less, IREF1mA is recommended. Low reference current operation decreases power consumption and increases negative
SETTLING TIME
The AM6012 is capable of extremely fast settling times, typically 250ns at IREF=1.0mA. Judicious circuit design and careful board layout must be employed to obtain full performance potential during
August 31, 1994
780
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
testing and application. The logic switch design enables propagation delays of only 25ns for each of the 12 bits. Settling time to within LSB of the LSB is therefore 25ns, with each progressively larger bit taking successively longer. The MSB settles in 250ns, thus determining the overall settling time of 250ns. Settling to 10-bit accuracy requires about 90 to 130ns. The output capacitance of the AM6012 including the package is approximately 20pF; therefore, the output RC time constant dominates settling time if RL>500. Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for IREF values down to 0.5mA, with gradual increases for lower IREF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve 2A, therefore a 2.5k load is needed to provide adequate drive for most oscilloscopes. At IREF values of less than 0.5mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 011111111111 to 100000000000 provides an accurate indicator of settling time. This code change does not require the normal 6.2 time constants to settle to within 0.1% of the final value, and thus settling times may be observed at lower values of IREF. AM6012 switching transients or "glitches" are very low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference, and VLC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1F capacitors at the supply pins provide full transient protection.
When a DC reference is used, a reference bypass capacitor is recommended. A 5.0V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R14 should be split into two resistors with the junction bypassed to ground with a 0.1F capacitor. For most applications, the tight relationship between IREF and IFS will eliminate the need for trimming IREF. If required, full-scale trimming may be accomplished by adjusting the value of R14, or by using a potentiometer for R14.
MULTIPLYING OPERATION
The AM6012 provides excellent multiplying performance with an extremely linear relationship between IFS and IREF over a range of 1mA to 1A. Monotonic operation is maintained over a typical range of IREF from 100A to 1.0mA.
REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS
reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to V-. The value of this capacitor depends on the impedance presented to Pin 14. For R14 values of 1.0, 2.5 and 5.0k, minimum values of CC are 5, 12 and 25pF. Larger values of R14 require proportionately increased values of CC for proper phase margin (see Figure 2b). For fastest response to a pulse, low values of R14 enabling small CC values should be used. If Pin 14 is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. For R14=1k and CC=5pF, the reference amplifier slews at 4mA/ms enabling a transition from IREF=0 to IREF=1mA in 250ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (IREF=0) condition. Full-scale transition (0 to 1mA) occurs in 62.5ns when the equivalent impedance at Pin 14 is 800 and CC=0. This yields a reference slew rate of 8mA/s which is relatively independent of RIN and VIN values.
APPLICATIONS INFORMATION Reference Amplifier Setup
The AM6012 is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to +1.0mA. The full range output current is a linear function of the reference current and is given by: I FR + 4095 x 4 x (I REF) + 3.999 I REF 4096
LOGIC INPUTS
The AM6012 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, 40A logic input current, and completely adjustable logic threshold voltage. For V-=-15V, the logic inputs may swing between -5 and +10V. This enables direct interface with +15V CMOS logic, even when the AM6012 is powered from a +5V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V- plus (IREFx3k) plus 1.8V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (Pin 13, VLC). For TTL interface, simply ground Pin 13. When interfacing ECL, an IREF1mA is recommended. For general setup of the logic control circuit, it should be noted that Pin 13 will sink 1.1mA typical. External circuitry should be designed to accommodate this current (Figure 3).
where IREF = I14 In positive reference applications, an external positive reference voltage forces current through R14 into the VREF(+) terminal (Pin 14) of the reference amplifier. Alternatively, a negative reference may be applied to VREF(-) at Pin 15. Reference current flows from ground through R14 into VREF(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at Pin 15. The voltage at Pin 14 is equal to and tracks the voltage at Pin 15 due to the high gain of the internal reference amplifier. R15 (nominally equal to R14) is used to cancel bias current errors (Figure 2a). Bipolar references may be accommodated by offsetting VREF or Pin 15. The negative common-mode range of the reference amplifier is given by: VCM-=V- plus (IREFx3k) plus 1.8V. The positive common-mode range is V+ less 1.23V.
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781
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
VR+
RIN VIN
R14 14 IREF
AM6012
REFERENCE AMPLIFIER IO 15 I15
18 IO + IO = IFS FOR ALL INPUT CODES IO 19
R15 = R14 = RIN VIN R15
COMP CC VR- V- V+ 0.1 V- 0.1 22F TANTALUM (NOTE 5)
20
REFERENCE CONFIGURATION Positive reference Negative reference Lo impedance bipolar reference Hi impedance bipolar reference Pulsed reference4
R14 VR+ 0V VR+ VR+ VR+
R15 0V VR- 0V VIN 0V
RIN N/C N/C VIN1 N/C1 VIN
CC 0.01F 0.01F
IREF VR+/R14 -VR-/R14 (VR+/R14) + (VIN/RIN)2 (VR+ - RIN) / R143
No Cap
(VR+/R14) + (VIN/RIN)
NOTES: 1. The compensation capacitor is a function of the impedance seen at the +VREF input and must be at least 5pF x R14(eq) in k. For R14 < 800 no capacitor is necessary. 2. For negative values of VIN, VR+ / R14 must be greater than -VIN max / RIN so that the amplifier is not turned off. 3. 4. 5. 6. For positive values of VIN, VR+ must be greater than -VIN max so the amplifier is not turned off. For pulsed operation, VR+ provides a DC offset and may be set to zero in some cases. The impedance at Pin 14 should be 800 or less. For optimum settling time, decouple V- with 20 and bypass with 22F tantalum capacitor. Reference current and reference resistor -- there is a 1-to-4 scale factor between the reference current (IREF) and the full-scale output current (IFS). If VREF = +10V and IFS = 4mA, the value of the R14 is:
R 14 +
4 x 10V 4mA
+ 10kW
R 14 + R 15
a. Reference Amplifier Biasing
Reference Amplifier Frequency Response Minimum Size Compensation Capacitor (IFS = 4mA, IREF = 1.0mA) R14(EQ) (k) 10 5 2 1 .5 CC (pF) 50 25 10 5 0 RELATIVE OUTPUT, dB 6 4 2 0 -2 -4 -6 -8 .01 SMALL SIGNAL = 1% MODULATION OF 2mA FULL SCALE CURRENT 0.1 1.0 10 LARGE SIGNAL = 50% MODULATION OF 4mA FULL SCALE CURRENT R14 (EQ) = 2k CC = 10pF
NOTE: A 0.01F capacitor is recommended for fixed reference operation.
FREQUENCY MHz
b. Figure 2. 782
August 31, 1994
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
ECL CMOS, HTL
V+
20k "A" 2N3904 2N3904 3k 20k R "A"
13k 2N3904 2N3904 3k TO PIN 13 VLC 400A 39k TO PIN 13 VLC 6.2k
-5.2V NOTE: 1. Set the voltage `A' to the desired logic input switching threshold. 2. Allowable range of logic threshold is typically -5V to +13.5V when operating the DAC on 15V supplies.
Figure 3. Interfacing Circuits for ECL, CMOS, HTL Logic Inputs
ACCOMMODATING BIPOLAR REFERENCE
VREF(+) RREF IREF 18 14 RIN AM6012 15 19 IREF > PEAK NEGATIVE SWING OF IIN NOTE: IREF > Peak negative swing of IIN. IO IO
BASIC NEGATIVE REFERENCE OPERATION
RREF 14 AM6012 VREF(-) R15 15 19 18 IO IO
IIN VIN
NOTE: I FS [
V REF(* R REF
) x4
RREF sets IFS; R15 is for a bias current cancellation.
RECOMMENDED FULL-SCALE ADJUSTMENT CIRCUIT
18 AM6012 IO IO 19 VREF(+) RREF = R15 VIN HIGH INPUT IMPEDANCE VREF+ MUST BE ABOVE PEAK POSITIVE SWING OF V IN RREF 14 AM6012 15 19 18 IO IO
VREF(+) RREF = R15 VIN
RREF
14 15
R15 (OPTIONAL)
R15 (OPTIONAL)
HIGH INPUT IMPEDANCE VREF MUST BE ABOVE PEAK POSITIVE SWING OF V IN
NOTE: VREF(+) Must be above peak positive swing of VIN.
August 31, 1994
783
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
APPLICATION CIRCUITS
5,000k ROFF R3 f R14 10k VREF(+) AM6012 R15 10k VREF(-) B1 B12 IO b g R2 IO a d e c - NE535 + VOUT R1 2.000mA
+10V REF
R 14 +
V REF
OPTIONAL (SEE CODE TABLE)
1.0mA V REF R + OFF 2.0mA
MSB
LSB
CODE FORMAT Straight binary; one polarity with true input code, true zero output. Unipolar Complementary binary; one polarity with complementary input code, true zero output. Straight offset binary; offset half-scale, symmetrical about zero, no true zero output.
CONNECTIONS a-c b-g R1 = R2 = 2.5k a-g b-c R1 = R2 = 2.5k
OUTPUT SCALE Positive full-scale Positive full-scale - LSB Zero-scale Positive full-scale Positive full-scale - LSB Zero-scale
MSB B1 B2 1 1 0 0 0 1 1 1 0 0 0 1
B3 1 1 0 0 0 1
B4 1 1 0 0 0 1
B5 1 1 0 0 0 1
B6 1 1 0 0 0 1
B7 1 1 0 0 0 1
B8 1 1 0 0 0 1
B9 1 1 0 0 0 1
LSB B10 B11 B12 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1
IO (mA) 3.999 3.998 0.000 0.000 0.001 3.999
IO (mA) 0.000 0.001 3.999 3.999 3.998 0.000
VOUT 9.9976 9.9951 0.0000 9.9976 9.9951 0.0000
a-c b-d f-g R1 = R3 = 2.5k R2 = 1.25k
Positive full-scale Positive full-scale - LSB (+) Zero-scale (-) Zero-scale Negative full-scale - LSB Negative full-scale
1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0
1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0
3.999 3.998 2.000 1.999 0.001 0.000 3.999 3.998 2.000 1.999 0.001 0.000 3.999 3.998 2.001 2.000 1.999 0.001 0.000
0.000 0.001 1.999
9.9976 9.9927 0.0024
2.000 -0.0024 3.998 -9.9927 3.999 -9.9976 0.000 0.001 1.999 9.9976 9.9927 0.0024
Symmetrical Offset
1's complement; offset half-scale, symmetrical about zero, no true zero output, MSB complemented (need inverter at B1).
a-c b-d f-g R1 = R3 = 2.5k R2 = 1.25k
Positive full-scale Positive full-scale - LSB (+) Zero-scale (-) Zero-scale Negative full-scale - LSB Negative full-scale
2.000 -0.0024 3.998 -9.9927 3.999 -9.9976 0.000 0.001 1.998 1.999 9.9951 9.9902 0.0049 0.000
Offset binary; offset halfscale, true zero output.
e-a-c b-g R1 = R2 = 5k
Positive full-scale Positive full-scale - LSB + LSB Zero-scale - LSB Negative full-scale + LSB Negative full-scale
2.000 -0.0049 3.998 -9.9951 3.999 -10.000
Offset with True Zero
2's complement; offset half-scale, true zero output, MSB complemented (need inverter at B1).
e-a-c b-g R1 = R2 = 5k
Positive full-scale Positive full-scale - LSB + 1 LSB Zero-scale - 1 LSB Negative full-scale + LSB Negative full-scale
3.998 2.001 2.000 1.999 0.001 0.000
0.001 1.998 1.999 2.000
9.9902 0.0049 0.000 -0.049
3.998 -9.9951 3.999 -10.000
Figure 4. AM6012 Logic Inputs
ADDITIONAL CODE MODIFICATIONS
1. Any of the offset binary codes may be complemented by reversing the output terminal pair.
August 31, 1994
784
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
APPLICATION CIRCUITS
+120VDC
60V COMMON MODE LEVEL CRT
"X" INPUT
"Y" INPUT
IO AM6012 -15V -15V IO
IO AM6012
IO
NOTES: 1. Full differential drive lowers power supply voltage. 2. Eliminates inverting amplifiers and transformers. 3. Independent beam centering controls.
Figure 5. CRT Display Driver
CONVERSION TIME vs ACCURACY 1.25
E CLOCK CP Q11
S CC 2504 SAR (NAT'L, AMD)
DO D O0 LSB
ACCURACY, LSB
SERIAL DATA OUT
1.00 (WORST CASE) AM6012 WITH NE529 AM6012 WITH NE529 (TYP)
0.75
0.50
0.25 +15V ANALOG IN (0-10V) 0.00 100
VREF 10.000k
200 300 400 500 600 700 CONVERSION TIME PER TRIAL, ns
800
+10V REF
5.000k 5.000k
MSB MSB AM6012 COMP IO 0.001 0.001 F F LSB IO
2.5k
NE529 CONVERSION TIME (ns) SAR NE529 TOTAL X 13 TYP 33 100 383ns 5.0s WORST CASE 55 150 705ns 9.1s
0.1F 10.000k 0.01 F
1F
1F
V(-0
V(+)
Figure 6. 12-Bit High-Speed A/D Converter
August 31, 1994
785
Philips Semiconductors Linear Products
Product specification
12-Bit multiplying D/A converter
AM6012
APPLICATION CIRCUITS
OE 7 6 5 P BUS 4 3 2 1 0 6012 LS373 MSB
E2 E1 EB D3A D2A D1A D0A EA 1/2LS100 Q3A Q2A Q1A Q0A D3B D2B D1B D0B 1/2LS100 Q3B Q2B Q1B Q0B LSB
a. Interface With 8-Bit Microprocessor Bus
E1
E2
NOTE: Data remains on inputs of DAC until updated by E2 pulse. Timing will depend on processor used.
August 31, 1994
EEEEEEEEEEEEE EE E E EEEEEEEEEEEEE EE E E EEEEEEEEEEEEE EE E E EEEEEEEEEEEEE EE E E
DB0-3 DB4-11
a. Timing Sequence
Figure 7.
786

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